1. Technical Field
The present disclosure relates generally to methods and apparatuses for clock and data recovery (CDR). In particular, the present disclosure relates to methods and apparatuses suitable for recovering a clock signal upon receipt of an input data signal, and further providing a retimed data signal based on the clock signal and the input data signal.
2. Discussion of Technical Background
A CDR circuit has been widely used in a telecommunication system. Upon receipt of a Non Return to Zero (NRZ) data signal, the CDR circuit may be used to recover a clock signal associated with the NRZ data signal, and further retime the received NRZ data signal based on the recovered clock signal. Alternatively or in addition to a phase-locked loop (PLL) circuit, a frequency-locked loop (FLL) circuit may be included in the CDR circuit to perform the clock recovery operation. The FLL circuit may be used to lock a frequency of the clock signal to a frequency of the NRZ data signal. Alternatively, the FLL circuit, in some other configurations, may be used to lock the frequency of the clock signal to a division of the frequency of the NRZ data signal.